A transmitter circuit employing a PLL is described, for example, in non-patent documents 1 to 3. Each of them is a transmitter-receiver system, which calibrates a loop band-width with a fractional-N PLL.
Firstly, the transmitter-receiver system of non-patent document 1 inputs an 0101 pattern by the data signal from the base band as a signal for detecting the loop band-width, and inputs it into the fractional-N PLL. The loop band-width is detected by monitoring the output of a voltage controlled signal source.
In the transmitter-receiver system of non-patent document 2, the signal to detect the loop band-width utilizes the transmitting data signal. As for the detecting method, by monitoring the output of a voltage controlled signal source and digitizing the phase component, the signal is compared with the data signal from the base band, further integrated to detect the loop band-width.
The invention, according to non-patent document 3, is intended for the calibration system of the loop band-width in the fractional-N PLL. For the signal to detect the loop band-width, a step signal is input into the divider through a sigma delta modulator in the PLL. In this case, the feedback input signal has a phase transition in the phase detector.
On the other hand, in non-patent document 4, a transmitter-receiver system is disclosed which performs the calibration of the loop band-width in the Digital Frequency Locked Loop. In this case, the calibration of the loop band-width is conducted by using a charge pump type DA converter and loop filter, two different voltages being given to a voltage controlled power source, and detecting the gain in the voltage controlled power source by the frequency change therefrom.
Non-patent document 1: S. T. Lee et al., “A 1.5V 2.8 mA Fully-Integrated Fast-Locking Quad-Band GSM-GPRS Transmitter with Digital Auto-Calibration in 130 nm CMOS”, IS SCC Dig. Tech. Papers, pp 188-189 (February 2004)
Non-patent document 2: D. R. McMahill and C. G. Sodini, “A 2.5-Mb/s GFSK 5.0-Mb/s 4-FSK Automatically Calibrated Sigma Delta Frequency Synthesizer” IEEE Journal of Solid State Circuit (January 2002)
Non-patent document 3: Yukinori Akamine et al., “A Loop Bandwidth Calibration System for Fractional-N System for Fractional-N Synthesizer and ΔΣPLL Transmitter” Session 17.4 ISSCC 2005 (February 2005)
Non-patent document 4: Bill Huff, “A fully-integrated Bluetooth synthesizer using digital pre-distortion for PLL-based GFSK modulation” 2003 IEEE RFIC symposium (June 2003)